Field
This disclosure relates generally to data processing systems, and more specifically, to message filtering in a data processing system.
Related Art
In a multiple processor data processing systems, inter-processor interrupt messaging allows a processor to send an interrupt message to other processors or devices within the data processing system. For example, a processor can initiate a message send instruction which specifies both a message type and message payload in a general purpose register. This message is sent to all processors and devices, including the sending processor) within a particular domain. Each processor and device receives all sent messages and upon receipt of each message, the processor or device examines the message type and payload to determine whether the device or processor should accept the message. If a message is accepted, the accepting processor or device takes specified actions based on the message type. This inter-processor interrupt messaging requires each processor or device to have the ability to locally determine whether a message is accepted. Also, a delivery mechanism is required to deliver all messages to all processors and devices. In one such system, inter-processor interrupt messaging is performed within a memory coherency domain in which cache coherency snooping mechanisms are used to implement the messaging. However, these cache coherency snooping mechanisms are not available in all systems. Other systems utilize an independent distributed messaging interface between multiple processors in the system. However, this results in increased cost. Therefore, a need exist for an improved interrupt messaging system.